RegViz: Visualize GTPSR Bitfield

Renesas Electronics /R7FA4M2AD /GPT320 /GTPSR

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Interpret as GTPSR

PSELCD=0, PSGTRGBR=0, CSTOP=0, PSCBRAL=0, PSGTRGAR=0, PSGTRGCF=0, PSELCB=0, PSCAFBH=0, PSGTRGAF=0, PSELCA=0, PSCARBH=0, PSCARBL=0, PSGTRGDF=0, PSELCG=0, PSELCF=0, PSELCE=0, PSCAFBL=0, PSCBFAH=0, PSCBRAH=0, PSGTRGDR=0, PSELCH=0, PSELCC=0, PSCBFAL=0, PSGTRGCR=0, PSGTRGBF=0

Description

General PWM Timer Stop Source Select Register

Fields

PSGTRGAR	GTETRGA Pin Rising Input Source Counter Stop Enable 0 (0): Counter stop disabled on the rising edge of GTETRGA input 1 (1): Counter stop enabled on the rising edge of GTETRGA input
PSGTRGAF	GTETRGA Pin Falling Input Source Counter Stop Enable 0 (0): Counter stop disabled on the falling edge of GTETRGA input 1 (1): Counter stop enabled on the falling edge of GTETRGA input
PSGTRGBR	GTETRGB Pin Rising Input Source Counter Stop Enable 0 (0): Counter stop disabled on the rising edge of GTETRGB input 1 (1): Counter stop enabled on the rising edge of GTETRGB input
PSGTRGBF	GTETRGB Pin Falling Input Source Counter Stop Enable 0 (0): Counter stop disabled on the falling edge of GTETRGB input 1 (1): Counter stop enabled on the falling edge of GTETRGB input
PSGTRGCR	GTETRGC Pin Rising Input Source Counter Stop Enable 0 (0): Counter stop disabled on the rising edge of GTETRGC input 1 (1): Counter stop enabled on the rising edge of GTETRGC input
PSGTRGCF	GTETRGC Pin Falling Input Source Counter Stop Enable 0 (0): Counter stop disabled on the falling edge of GTETRGC input 1 (1): Counter stop enabled on the falling edge of GTETRGC input
PSGTRGDR	GTETRGD Pin Rising Input Source Counter Stop Enable 0 (0): Counter stop disabled on the rising edge of GTETRGD input 1 (1): Counter stop enabled on the rising edge of GTETRGD input
PSGTRGDF	GTETRGD Pin Falling Input Source Counter Stop Enable 0 (0): Counter stop disabled on the falling edge of GTETRGD input 1 (1): Counter stop enabled on the falling edge of GTETRGD input
PSCARBL	GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable 0 (0): Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 1 (1): Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
PSCARBH	GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable 0 (0): Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 1 (1): Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
PSCAFBL	GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable 0 (0): Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 1 (1): Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
PSCAFBH	GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable 0 (0): Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 1 (1): Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
PSCBRAL	GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 0 (0): Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 1 (1): Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
PSCBRAH	GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable 0 (0): Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 1 (1): Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
PSCBFAL	GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable 0 (0): Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 1 (1): Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
PSCBFAH	GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable 0 (0): Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 1 (1): Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
PSELCA	ELC_GPTA Event Source Counter Stop Enable 0 (0): Counter stop disabled at the ELC_GPTA input 1 (1): Counter stop enabled at the ELC_GPTA input
PSELCB	ELC_GPTB Event Source Counter Stop Enable 0 (0): Counter stop disabled at the ELC_GPTB input 1 (1): Counter stop enabled at the ELC_GPTB input
PSELCC	ELC_GPTC Event Source Counter Stop Enable 0 (0): Counter stop disabled at the ELC_GPTC input 1 (1): Counter stop enabled at the ELC_GPTC input
PSELCD	ELC_GPTD Event Source Counter Stop Enable 0 (0): Counter stop disabled at the ELC_GPTD input 1 (1): Counter stop enabled at the ELC_GPTD input
PSELCE	ELC_GPTE Event Source Counter Stop Enable 0 (0): Counter stop disabled at the ELC_GPTE input 1 (1): Counter stop enabled at the ELC_GPTE input
PSELCF	ELC_GPTF Event Source Counter Stop Enable 0 (0): Counter stop disabled at the ELC_GPTF input 1 (1): Counter stop enabled at the ELC_GPTF input
PSELCG	ELC_GPTG Event Source Counter Stop Enable 0 (0): Counter stop disabled at the ELC_GPTG input 1 (1): Counter stop enabled at the ELC_GPTG input
PSELCH	ELC_GPTH Event Source Counter Stop Enable 0 (0): Counter stop disabled at the ELC_GPTH input 1 (1): Counter stop enabled at the ELC_GPTH input
CSTOP	Software Source Counter Stop Enable 0 (0): Counter stop disabled by the GTSTP register 1 (1): Counter stop enabled by the GTSTP register

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